The present disclosure relates to semiconductor structures, and, more specifically, to memory cells with write-assist structures and methods of use.
Random access memory (RAM) may be static or dynamic. Static random access memory (SRAM) is a type of semiconductor memory used in many integrated circuit applications, which uses bi-stable latching circuitry to store each bit. SRAM is a desirable type of memory due to its high-speed, low power consumption, and simple operation. The term static differentiates it from dynamic random access memory (DRAM), which must be periodically refreshed. Unlike DRAM, SRAM does not need to be regularly refreshed to retain the stored data.
A typical SRAM cell includes a pair of cross-coupled inverters that hold a desired data bit value (i.e., either a 1 or a 0) and the complement of that value. An SRAM cell has three different states: standby, read and write. In order for the SRAM to operate in read mode and write mode, it should have “readability” and “write stability” respectively. Readability of an SRAM cell is the ability to drive a required signal magnitude onto the bitline within a specified time allocated for signal development, and is a function of the read current of the cell. Typically, write operations limit the cycle time in an SRAM. A conventional write driver may have write assist with a stack of transistors for discharging the bitline (BL). The greater the number of transistors in the path of the BL to the write driver, the slower will be the pull down of the BL during write operations. With higher numbers of cells per bitline, the RC time constant associated with the bitline aggravates this issue even further.
In SRAM, write assist may be needed to improve the ability to write to a memory cell at low voltages. Enabling write assist at higher voltages (>0.9 v), however, may be a reliability concern, so write assist is typically enabled only at lower voltages (<0.7 v). Conventional write assist impacts the cycle time even when it is not enabled due to the additional transistor device it adds to the write driver pull down stack. Furthermore, conventional write assist is tightly integrated to current circuit designs, such that changes may result in an area penalty even when it is not used for write operations. That is, the circuit design would have to be extensively reworked to strip out the write assist and save area. Accordingly, there remains a need for a write assist circuit that can be added as an extra block of logic to an already existing design without circuit disruption.